Logic Simulator

This Logic Simulator incorporates Verilog-like logic hardware description language and simulator into the Wolfram language. This has the advantage that the full Wolfram language is available for hardware description and analyses. It also provides the Mathematica user with a hardware description capability without having to learn yet another programming language. The disadvantage is that it is not compatible with other hardware design tools.

I wrote this hardware simulator to investigate finite state machines. To keep things simple I have not included timing analysis.
(I didn't manage to get this into the original post)