hi johan,
I do not have latest system modeler 4.0.1, i have system modeler 4.0 but i think it will not matter. and also thanks for attaching the output plot
but if you will notice, the input on data line is a pulse. the output should be pulse delayed by 1 clock period, whereas the output is coming the clock itself. please check and let me know if i am wrong
regards
manu
