User Portlet
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| no john, if you will see this is not a block, but the modelica language script. the question is how in script i can allot a logic value '1' to a digital signal |
| thanks it worked why RAM takes so many equations and variables. it should be just a look up table |
| if i have got many components to be a part of my subsystem, how can i increase drawing area with grid of my model/project to accommodate all components. |
| you missed the point. idea was not normalization. it is just a multiplication. the harmonics and spurious came pronouncingly only in dB plot but not otherwise. however, i think when you develop next version you can debate of incorporating as part... |
| can somebody solve and describe me this error and under what circumstances it occurs. how to solve in this particular case ![simulation of DLATROM showing error][1] [1]: /c/portal/getImageAttachment?filename=7234ans1.png&userId=320464 |
| i ran your query in wolfram program cloud. see if it can help you. the output is also attached [1]: /c/portal/getImageAttachment?filename=7243ans1.png&userId=320464 |
| hi sir i am attaching the two files where i have tried simulating 2 by 2 ROM, both in binary and digital logic. it is giving me following error while running system modeler simulation centre ![error message][1] [1]:... |
| hi johan, I do not have latest system modeler 4.0.1, i have system modeler 4.0 but i think it will not matter. and also thanks for attaching the output plot but if you will notice, the input on data line is a pulse. the output should be pulse... |
| specifically boolean input port on reducing their size, the font size do not reduce. this causes problem in piling them. |
| hi david thankyou, it worked regards manu |